verilog_adaptive_filter_32_order

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adaptive-filter_32-order

View adaptive filter 32 order on GitHub.


This FPGA project is a 32 orders adaptive filter with s2p and p2s to communicate with Renesas RX210 MCU.

  1. Waveform overview : Input : mosi ; Output : miso
  2. Waveform algorithm top : Use basic FIFO structure to store 32 input dates and do 32 orders adaptive filter.
  3. Waveform s2p : Convert serial data input (miso) to Parallel data output (ad_1, ad_2).
  4. p2s : Convert parallel data input (in_p2s) to Serial data output (mosi).
  5. Waveform adaptive filter :
  6. Algorithm structure is based on this picture:

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